Abstract: Multilayer structures composed of different materials are widely used in microelectronic packaging. When temperature changes, thermal expansion mismatch of materials at different layers will lead to thermal warping, and excessive warping will lead to chip cracking, chip layering, solder joint failure and other packaging failure problems. Therefore, it is necessary to study the thermal warping of typical multilayer structure. In this paper, the thermal warpage measurement platform was built based on the three-dimensional digital image correlation method (DIC) to realize the real-time observation of thermal warping process of multilayer plate. In the heating process, the thermal warping of typical double-layer and triple-layer plates with different thicknesses and materials were measured respectively. Furthermore, the finite element simulation of thermal warping of multilayer plates was conducted according to experimental conditions, in which the temperature loading curve was obtained by modifying the measured temperature results by infrared thermal imager. The thermal warping simulation results and experimental results were compared. According to experimental and simulation results, the effects of plate thickness, material properties and number of layers on the thermal warpage value were discussed. Moreover, the warpage measurement technology based on DIC was used to measure the warpage value of a chip at room temperature, and the results were compared with that by using the white light interference method. The results show that the thermal warpage results of multilayer plates measured by DIC method are in good agreement with the simulation results in the heating process. And the variation of single layer material and thickness has great influence on warping. For the QFN128 package, the surface warpage results measured by DIC method and white light interference method at room temperature are consistent. The DIC method can provide an effective way to measure the thermal warpage of typical multilayer structures in microelectronic packaging.